SRAM cells are commonly used in the industry in the form of single port, dual port, and multiport memory cells. The performance of a memory cell is commonly measured by the read-access time and write time. Many factors influence these parameters. Among the primary factors are device drive currents and parasitic capacitances due to junctions, gates, and interconnects.
Read-access time is primarily influenced by the cell current and bitline capacitance. The writing of a data state into an SRAM cell is commonly performed by turning on the wordline and the driving the bitlines to mutually opposite rail voltages in order to force the internally contained latch to switch states. This operation is a strong function of a) the strength of the pass gate in relation to the pull-up device in the memory cell and b) the capacitance of the internal nodes of the memory cell.
The latter factor is of great importance and can be a limiting factor in the overall performance of a memory cell. This is especially true in the case of multiport memory cells (such as 6-port or 8-port), because multiport memory cells can have significantly higher internal node capacitances compared to single port memory cells. For example, the addition of each differential (dual-ended) write/read port entails at least the addition of some diffusion capacitance to the internal nodes, whereas the addition of each single-ended read port entails at least the addition of some gate capacitance at the internal node.
A large internal node capacitance can result in a situation where the switching of the internal nodes during writing can be extremely asymmetric with respect to time. For example, FIG. 1 is a graph showing the voltage behavior of two internal storage nodes of an SRAM cell during a write operation.
Typically, at a storage node, a voltage transition from a logical zero (“0”) to a logical one (“1”) is substantially slower than a voltage transition from a “1” to a “0”. Line 52 represents the behavior of one storage node transitioning from a “1” to a “0”. Line 54 represents the behavior of the other storage node transitioning from a “0” to a “1”. As shown, the “crossover” point can be extremely skewed due to the slow rise in voltage of a storage node. This is caused by high internal node capacitance within the memory cell. To enable a reliable write operation, the rising node needs to rise to a sufficiently high voltage before the wordlines are turned off. Consequently, the write speed slows down. Because this situation may be unavoidable, it is therefore important to be able to accurately predict and verify the transient AC behavior during a write operation.
There are multiple methods used to verify the electrical performance of a circuit. One conventional solution of verifying the DC electrical performance of an SRAM circuit is to obtain DC measurements of the individual transistor devices at different PVT (process, voltage and temperature) corners. These measurements can yield useful information for verifying the accuracy of the transistor SPICE models. However, a problem with this solution is that it does not address issues described above related to transient (AC) behavior.
The AC performance of circuits have been obtained using simple ring-oscillator structures. For the application at hand, that is, the verification of write speed of complex SRAM bitcells, a direct application of ring oscillator type of test structure has not been possible. This is because in order to conventionally access the internal node of a bitcell, an additional wire would have to be attached to it. The problem with this approach is that the wire itself would add internal node capacitance and alter the write characteristics of the bitcell.
Accordingly, what is needed is an improved circuit for verifying the write speed of SRAM cells. The system and method should be simple, cost effective and capable of being easily adapted to existing technology. The design of the test circuit should reflect the true layout of the SRAM bitcell array so that the design itself does not affect the measurement results. The present invention addresses such a need.